The low-density parity-check (LDPC) code is currently attracting attention as an error correcting code with error correction capacity extremely close to the Shannon limit that is theoretical limit of the information transfer rate. For example, many efforts are being made actively to implement the LDPC decoding apparatus using hardware, and to use the hardware implementation in communication systems and storage systems. While various types of LDPC code decoding algorithms are now available, the most popular decoding algorithm is the sum-product algorithm (SPA). The SPA is known to be a decoding algorithm with the highest error correction capacity.
However, when the scale of the circuit used for decoding LDPC codes is limited, or when the decoding apparatus has limited resources such as a memory that can be assigned to a computer program executing the LDPC code decoding, precise execution of the LDPC code decoding process has been difficult.